As circuit structure features have continued to shrink and become increasingly complex, circuit structure fabrication techniques have been continually modified to successfully form transistor features. Complex gate structures that span multiple fins, and have shapes more complex than simple rectangles, have generally been formed by single patterning processes at larger technology nodes. However, at current technology nodes of 10 nm or less, single patterning processes generally are not capable of accurately reproducing designed gate structures on a wafer, resulting in transistor structures that may not function properly.